Current testing of high density integrated circuits is accomplished by large, very expensive test apparatus. As is currently well known in the art, integrated circuits are evaluated by connecting the peripherally arranged input and output pads or traces of the integrated circuit to the test set via a probe card.
Typically, probe cards consist essentially of a circular or rectangular printed circuit board having a centrally located circular opening which provides access to the integrated circuit to be tested, one or more concentric rings of spaced conductive pads on the bottom side of the board surrounding the opening, and connector terminals connected to the conductive pads via conductive traces. A radial array of conductive probes, which are positioned to engage the traces of the integrated circuit under test, are attached at one end to the conductive pads and the distal end extends into the opening.
Generally, the probe pins are pressed against the pads to establish electrical contact. In some instances, the pins may be constructed to include mechanical switches, commonly referred to as edge sensors, which become open when probe pin contact of sufficient force to ensure conduction is established The open state informs the test system that the probe card is ready to test the integrated circuit.
Typically, the probe card is attached to the test instrumentation via a long cable. For high speed systems, the impedances within the test arrangement must be accurately matched and the signal time delays accounted for in order to perform accurate testing. A time domain reflectometer (TDR) is typically used to characterize the test system prior to testing The measured system anomalies can be removed from the recorded test data by extensive signal processing once the data has been recorded or compensation and adjustment can be applied while the data is being collected. In either case, having the test apparatus, i.e., the test signal drive circuits and the test signal response sampling circuits, located a distance from the device under test is undesirable.
Additionally, test circuitry used to evaluate integrated circuits must be easily configurable at the user's firm to meet the specific needs of the device under test. Thus, the test signal drive circuits and the test signal response sampling circuits which are connected to the probes via the long cable must be oriented to match the specific nature of integrated circuit terminal under tested. In other words, the integrated circuits input circuits must be aligned with a test probe which is connected to a test signal drive circuit and the output circuits must be aligned with the test signal sampling circuits.
In an effort to standardize test procedures concerning on-board testing of integrated circuits, the Institute of Electrical and Electronic Engineers (IEEE) promulgated the IEEE Standard Test Access Port and Boundary-Scan Architecture, as described in the document IEEE Std. 1149.1, and incorporated herein by reference. The standard was developed by the Joint Test Action Group (JTAG) and has become known in the integrated circuit industry as the JTAG standard. This standard is adaptable to provide versatile test apparatus which can be configured by the user. An integrated circuit adapter as disclosed in U.S. patent application Ser. No. 07/650,692, entitled "Integrated Circuit Test Adapter" now U.S. Pat. No. 5,096,266 teaches apparatus which configures the JTAG boundary-scan test circuitry to fulfill the current needs of the device under test. This application in herein incorporated by reference.
The specified technique enables integrated circuits to be tested using boundary-scan methodology after the integrated circuits have been permanently installed on a circuit board. However, the JTAG standard circuitry can be adapted to be incorporated into a probe card, creating an active probe card.
The present invention is an active probe card having boundary-scan test circuitry attached directly to the probe pins. In this arrangement, the test circuitry is not separated from the device under test. Therefore, costly time delay and impedance mismatch compensation circuitry is eliminated from the test arrangement.
An objective of the present invention is to enable the testing to be controlled by a workstation or personal computer. Boundary-scan test techniques are especially amenable to control by workstations and personal computers.
Another objective of the present invention is to provide a versatile probe card which can have the test pin orientations, i.e., input or output, programmed in the field to match a specific device under test.
Another object of the present invention is to provide a probe card which includes boundary-scan test circuitry, but also can be operated in conjunction with Automatic Test Equipment (ATE). Thus, a probe card mode of operation which makes the boundary scan circuitry invisible to other test circuitry is necessary.